Altium

Design Rule Verification Report

Date: 27/04/2018
Time: 12:01:39
Elapsed Time: 00:00:01
Filename: C:\Users\Labo\Documents\Projet\PCB_Project\PCB1.PcbDoc
Warnings: 0
Rule Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (InNet('NetM1_3')),(All) 0
Clearance Constraint (Gap=10mil) (InNet('NetJ1_1')),(All) 0
Clearance Constraint (Gap=0mil) (InNet('IN+')),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=30mil) (All),(All) 0
Width Constraint (Min=8mil) (Max=20mil) (Preferred=20mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 4
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 4

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Track (3155mil,5301mil)(3155mil,5310mil) Top Overlay Pad R1-2(3155mil,5260mil) Multi-Layer
Track (3155mil,5510mil)(3155mil,5519mil) Top Overlay Pad R1-1(3155mil,5560mil) Multi-Layer
Track (2985mil,5010mil)(2994mil,5010mil) Top Overlay Pad R2-2(3035mil,5010mil) Multi-Layer
Track (2776mil,5010mil)(2785mil,5010mil) Top Overlay Pad R2-1(2735mil,5010mil) Multi-Layer
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