Altium

Design Rule Verification Report

Date: 27/04/2018
Time: 14:06:49
Elapsed Time: 00:00:00
Filename: C:\Users\Labo\Desktop\Labo6 AS-Ni\PCB_Project\PCB1.PcbDoc
Warnings: 0
Rule Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.127mm) ((InNet('VDD') OR InNet('NetM1_14') OR InNet('NetJ2_1'))),(All) 0
Clearance Constraint (Gap=0.127mm) (InNet('VOUT')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 4
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Silk primitive without silk layer 0
Net Antennae (Tolerance=0mm) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.203mm) (Max=0.508mm) (Preferred=0.508mm) (All) 0
Clearance Constraint (Gap=0.8mm) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Total 4

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Track (71.374mm,91.211mm)(71.374mm,91.44mm) Top Overlay Pad R1-1(71.374mm,90.17mm) Multi-Layer
Track (71.374mm,96.52mm)(71.374mm,96.749mm) Top Overlay Pad R1-2(71.374mm,97.79mm) Multi-Layer
Track (99.949mm,91.211mm)(99.949mm,91.44mm) Top Overlay Pad R2-1(99.949mm,90.17mm) Multi-Layer
Track (99.949mm,96.52mm)(99.949mm,96.749mm) Top Overlay Pad R2-2(99.949mm,97.79mm) Multi-Layer

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