Altium

Design Rule Verification Report

Date: 4/30/2018
Time: 1:12:52 PM
Elapsed Time: 00:00:00
Filename: F:\Documents\ULB\ELECH402\2017-2018\Labo 6 - Altium\Students\5\kenzo\PCBALTIUM\PCB1.PcbDoc
Warnings: 0
Rule Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 4
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Silk primitive without silk layer 0
Net Antennae (Tolerance=0mm) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.203mm) (Max=0.5mm) (Preferred=0.5mm) (All) 0
Clearance Constraint (Gap=0.8mm) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Clearance Constraint (Gap=0.127mm) (InNet('VDD')),(All) 0
Clearance Constraint (Gap=0.127mm) (InNet('NetM1_1')),(All) 0
Clearance Constraint (Gap=0.127mm) (InNet('VDD') or InNet('NetM3_9')),(All) 0
Total 4

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Track (66.192mm,106.934mm)(66.421mm,106.934mm) Top Overlay Pad R4-1(65.151mm,106.934mm) Multi-Layer
Track (71.501mm,106.934mm)(71.73mm,106.934mm) Top Overlay Pad R4-2(72.771mm,106.934mm) Multi-Layer
Track (89.535mm,84.226mm)(89.535mm,84.455mm) Top Overlay Pad R3-1(89.535mm,83.185mm) Multi-Layer
Track (89.535mm,89.535mm)(89.535mm,89.764mm) Top Overlay Pad R3-2(89.535mm,90.805mm) Multi-Layer

Back to top