Altium

Design Rule Verification Report

Date: 8/05/2018
Time: 17:11:14
Elapsed Time: 00:00:00
Filename: C:\Users\Public\Documents\Altium\Projects\PCB_John_Max\Project Logs for PCB_John_Max\PCB1.PcbDoc
Warnings: 0
Rule Violations: 6

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 6
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk primitive without silk layer 0
Net Antennae (Tolerance=0mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (All) 0
Clearance Constraint (Gap=30mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Total 6

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Track (3416mil,3265mil)(3425mil,3265mil) Top Overlay Pad R2-1(3375mil,3265mil) Multi-Layer
Track (3625mil,3265mil)(3634mil,3265mil) Top Overlay Pad R2-2(3675mil,3265mil) Multi-Layer
Track (3121mil,4520mil)(3130mil,4520mil) Top Overlay Pad R1-1(3080mil,4520mil) Multi-Layer
Track (3330mil,4520mil)(3339mil,4520mil) Top Overlay Pad R1-2(3380mil,4520mil) Multi-Layer
Track (3121mil,4760mil)(3130mil,4760mil) Top Overlay Pad R3-1(3080mil,4760mil) Multi-Layer
Track (3330mil,4760mil)(3339mil,4760mil) Top Overlay Pad R3-2(3380mil,4760mil) Multi-Layer

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