Altium

Design Rule Verification Report

Date: 8/05/2018
Time: 16:45:10
Elapsed Time: 00:00:01
Filename: C:\Users\Labo\Desktop\LaboElecAnalPCB\PCB_Project_Cyp_et_Mat\PCB2.PcbDoc
Warnings: 0
Rule Violations: 7

Summary

Warnings Count
Total 0

Rule Violations Count
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=30mil) (All),(All) 0
Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 7
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 7

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Track (3430mil,4170mil)(3439mil,4170mil) Top Overlay Pad R1-2(3480mil,4170mil) Multi-Layer
Track (3221mil,4170mil)(3230mil,4170mil) Top Overlay Pad R1-1(3180mil,4170mil) Multi-Layer
Track (2870mil,3975mil)(2870mil,3984mil) Top Overlay Pad R2-2(2870mil,4025mil) Multi-Layer
Track (2870mil,3766mil)(2870mil,3775mil) Top Overlay Pad R2-1(2870mil,3725mil) Multi-Layer
Text "P1" (2821mil,3629mil) Top Overlay Pad R2-1(2870mil,3725mil) Multi-Layer
Track (3695mil,4110mil)(3695mil,4119mil) Top Overlay Pad R3-2(3695mil,4160mil) Multi-Layer
Track (3695mil,3901mil)(3695mil,3910mil) Top Overlay Pad R3-1(3695mil,3860mil) Multi-Layer

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