Altium

Design Rule Verification Report

Date: 8/05/2018
Time: 16:51:55
Elapsed Time: 00:00:00
Filename: C:\Users\Labo\Desktop\WIWI PCB PROJECT NANA\PCB_ProjectNATAHETWILLIAM\PCB3.PcbDoc
Warnings: 0
Rule Violations: 6

Summary

Warnings Count
Total 0

Rule Violations Count
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Clearance Constraint (Gap=0.8mm) (All),(All) 0
Width Constraint (Min=0.5mm) (Max=0.5mm) (Preferred=0.5mm) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mm) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 6
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 6

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Track (90.805mm,87.147mm)(90.805mm,87.376mm) Top Overlay Pad R1-2(90.805mm,86.106mm) Multi-Layer
Track (90.805mm,92.456mm)(90.805mm,92.685mm) Top Overlay Pad R1-1(90.805mm,93.726mm) Multi-Layer
Track (84.582mm,121.539mm)(84.582mm,121.768mm) Top Overlay Pad R2-2(84.582mm,122.809mm) Multi-Layer
Track (84.582mm,116.23mm)(84.582mm,116.459mm) Top Overlay Pad R2-1(84.582mm,115.189mm) Multi-Layer
Track (70.231mm,89.814mm)(70.231mm,90.043mm) Top Overlay Pad R4-2(70.231mm,88.773mm) Multi-Layer
Track (70.231mm,95.123mm)(70.231mm,95.352mm) Top Overlay Pad R4-1(70.231mm,96.393mm) Multi-Layer

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