Altium

Design Rule Verification Report

Date: 8/05/2018
Time: 16:59:17
Elapsed Time: 00:00:00
Filename: C:\Users\Labo\Documents\PCB3_LA.PcbDoc
Warnings: 0
Rule Violations: 7

Summary

Warnings Count
Total 0

Rule Violations Count
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=30mil) (All),(All) 0
Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 6
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Un-Routed Net Constraint ( (All) ) 1
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 7

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Track (2831mil,4300mil)(2840mil,4300mil) Top Overlay Pad R5-2(2790mil,4300mil) Multi-Layer
Track (3040mil,4300mil)(3049mil,4300mil) Top Overlay Pad R5-1(3090mil,4300mil) Multi-Layer
Track (3045mil,3461mil)(3045mil,3470mil) Top Overlay Pad R7-2(3045mil,3420mil) Multi-Layer
Track (3045mil,3670mil)(3045mil,3679mil) Top Overlay Pad R7-1(3045mil,3720mil) Multi-Layer
Track (2841mil,4020mil)(2850mil,4020mil) Top Overlay Pad R8-2(2800mil,4020mil) Multi-Layer
Track (3050mil,4020mil)(3059mil,4020mil) Top Overlay Pad R8-1(3100mil,4020mil) Multi-Layer

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Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net NetC3_1 Between Track on layer Bottom Layer (3240,4765mil) And Pad M4-4 (3340,4765mil)

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