Altium

Design Rule Verification Report

Date: 8/05/2018
Time: 17:08:40
Elapsed Time: 00:00:00
Filename: C:\Users\Labo\Desktop\MSE\PCB2.PcbDoc
Warnings: 0
Rule Violations: 6

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 6
Silk to Silk (Clearance=10mil) (All),(All) 0
Silk primitive without silk layer 0
Net Antennae (Tolerance=0mil) (All) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (All) 0
Clearance Constraint (Gap=30mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Total 6

Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Track (3650mil,4141mil)(3650mil,4150mil) Top Overlay Pad R6-2(3650mil,4100mil) Multi-Layer
Track (3650mil,4350mil)(3650mil,4359mil) Top Overlay Pad R6-1(3650mil,4400mil) Multi-Layer
Track (2815mil,3660mil)(2815mil,3669mil) Top Overlay Pad R5-2(2815mil,3710mil) Multi-Layer
Track (2815mil,3451mil)(2815mil,3460mil) Top Overlay Pad R5-1(2815mil,3410mil) Multi-Layer
Track (3430mil,3876mil)(3430mil,3885mil) Top Overlay Pad R7-2(3430mil,3835mil) Multi-Layer
Track (3430mil,4085mil)(3430mil,4094mil) Top Overlay Pad R7-1(3430mil,4135mil) Multi-Layer

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